Lead frame land grid array with routing connector trace under unit

ABSTRACT

A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

RELATED APPLICATIONS

This application is a Divisional of co-pending U.S. patent applicationSer. No. 13/040,112, filed on Mar. 3, 2011, and entitled “LEAD FRAMELAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT,” which ishereby incorporated by reference. The U.S. patent application Ser. No.13/040,112, filed on Mar. 3, 2011, and entitled “LEAD FRAME LAND GRIDARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT” is a Continuation In Partand claims priority under 35 U.S.C. §120 of U.S. patent application Ser.No. 11/731,522, filed Mar. 30, 2007, entitled “LEAD FRAME LAND GRIDARRAY,” which in turn claims benefit of priority under 35 U.S.C. section119(e) of U.S. Provisional Patent Application 60/795,929, filed Apr. 28,2006, all of which are incorporated herein by reference. The U.S. patentapplication Ser. No. 13/040,112, filed on Mar. 3, 2011, and entitled“LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT”also claims priority under 35 U.S.C. section 119(e) of U.S. ProvisionalPatent Application 61/321,060, filed Apr. 5, 2010, which is incorporatedherein by reference.

FIELD OF THE INVENTION

The present invention is related to the field of semiconductorpackaging. More specifically, the present invention is directed to leadframe land grid array (LLGA).

BACKGROUND

The art of surface mount technologies for some semiconductor packages,is developing at a rapid pace. For instance, the following set ofcontinuation-in-part and divisional patents describes one suchdeveloping lineage. In particular, U.S. Pat. No. 6,072,239 to Yoneda, etal., entitled “Device Having Resin Package with Projection” (Yoneda'239) claims, among other things, a device having a chip, a resinpackage sealing the chip, metallic films, and connecting parts. Theresin package has resin projections that are located on a mount-sidesurface of the resin package. The resin projections have surfaces thatare parallel to the mount-side surface of the resin package. Themetallic films are formed on the entire surfaces of the resinprojections.

U.S. Pat. No. 6,159,770 to Tetaka, et al., entitled “Method andApparatus for Fabricating Semiconductor Device,” (Tetaka '770) claims amethod of fabricating the semiconductor device of Yoneda '239. Tetaka'770 is a continuation-in-part of Yoneda '239.

U.S. Pat. No. 6,329,711 to Kawahara, et al., entitled “SemiconductorDevice and Mounting Structure,” (Kawahara '711) claims a semiconductordevice that has a semiconductor element, a resin package sealing thesemiconductor element, resin projections, metallic film parts,connecting members, and connection pads. Each of the metallic film partshas a single point that makes contact with a circuit board. Kawahara'711 is a continuation-in-part of Yoneda '239.

U.S. Pat. No. 6,376,921 to Yoneda, et al., entitled “SemiconductorDevice, Method for Fabricating the Semiconductor device, Leadframe andMethod for Producing the Leadframe” (Yoneda '921) claims a semiconductordevice that has a semiconductor element, a resin package sealing thesemiconductor element, resin projections, metallic film portions, andconnecting members. The resin projections protrude downward from amounting surface of the resin package. Yoneda '921 is acontinuation-in-part of Yoneda '239.

U.S. Pat. No. 6,573,121 to Yoneda, et al., entitled “SemiconductorDevice, Method for Fabricating the Semiconductor Device, Leadframe andMethod for Producing the Leadframe,” (Yoneda '121) claims a method ofproducing a lead frame used to fabricate the semiconductor device ofYoneda '921. Yoneda '121 is a division of Yoneda '921.

However, this patent family lineage describes fabricating semiconductorsby using numerous processing steps. Moreover, the packages produced bythe patents mentioned above have certain limitations in the art.

Furthermore, current trends in integrated circuit packaging require agreater number of leads or solder bumps in a smaller and thinner formfactor. To that end, the applicants have developed IC packagingtechnology relating to plating desired areas onto a metal substratethereby forming several plated areas that serve as contacts, leads, dieattach pads, or the like in Co Pending U.S. patent application Ser. No.12/688,602. However, as IC developers produce ICs having a larger numberof input/outputs (I/O), a greater number of contacts is required in thecorresponding IC package. As the density of the contacts, or leads, areincreased, what results is less robust IC packages. In some instances,the plated contacts or other structures peel away from the finished ICpackage. Such peeling is exacerbated by requirements of more thinpackages that in turn require more thin plating.

SUMMARY OF THE DISCLOSURE

A carrier, or semiconductor package, for a semiconductor die is providedherein. The carrier generally comprises several contact traces that rununderneath the die. The contact traces are plated onto a metalsubstrate, such as copper, and when the substrate is sacrificed, whatare left are the contact traces. Advantageously, the traces can be madeextremely thin. In combination with extremely thin semiconductor diebackgrinding techniques well known in the semiconductor manufacturingindustry, the semiconductor package and method for its manufacturedescribed herein enables packages in the thickness of fractions of amillimeter. Furthermore, support structures for the contact traces areprovided. The support structures serve to absorb heat during the processof mounting the package to an end application, absorbing stress appliedto the contact, and generally provide structural support to the contacttrace. The support structures can be formed in the same manufacturingsteps as the contact traces. As one result, the support structuresreduce occurrences of traces peeling away from the semiconductor packagewithout adding significant cost or additional manufacturing steps.

In one aspect of the invention, a semiconductor package comprises aplurality of contact traces each having a first and second end, a firstsemiconductor die, and a resin encapsulant for encapsulating at least aportion of the plurality of contact traces and first semiconductor die,wherein the contact traces are arranged substantially underneath thesemiconductor die. The first ends of the contact traces are coupled withwirebonds for forming electrical connections with the semiconductor die,and the second ends are used to form electrical connections with an endapplication, such as a printed circuit board. In some embodiments, thesecond ends of the contract traces each comprise a contact padconfigured to receive a solder ball. Preferably, each contact padcomprises at least one support structure. The support structure can beof a variety of shapes, having arcuate or linear features, extendoutward from the second end of the contact trace, or at least partiallycircumscribes or surrounds the second end of the contact trace. In someembodiments, The package further comprises a second semiconductor diecoupled to the first semiconductor die, wherein the second semiconductordie is coupled to the wirebonding end of at least one contact trace by abondwire. Alternatively, the second semiconductor die is coupled to thefirst semiconductor die by a solder bump.

In another aspect of the invention, a method of forming a semiconductorpackage comprises plating a plurality of contact traces on a metalsubstrate, each contact trace having a first end and a second end,mounting semiconductor die substantially above the second ends of thecontact traces, removing the metal layer, thereby exposing the contacttraces, and singulating individual semiconductor die. Preferably, themethod further comprises forming at least one support structure aboutthe second end of at least one contact trace. In some embodiments, thestep of forming support structures comprises forming at least one platedarea extending outward from the second end of the at least one contacttrace. Alternatively, the step of forming support structures comprisesforming at least one plated area at least partially circumscribing thesecond end of the at least one contact trace.

In another aspect of the invention, a semiconductor device comprises asemiconductor die having an active surface and an inert surface, aplurality of contact traces routed underneath the inert surface, whereinthe contact traces comprise a plurality of plated layers, each contacttrace having a first end and a second end, at least one bondwire forelectrically coupling the first end of at least one contact trace to theactive surface of the semiconductor die, a resin encapsulant encasing atleast a portion of the semiconductor die and plurality of contacttraces, and a plurality of support structures formed about the secondends of the plurality of contact traces. The support structures can beformed to extend outward from the contact traces, at least partiallycircumscribe the contact traces, or a combination of both.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features of the invention are set forth in the appendedclaims. However, for purpose of explanation, several embodiments of theinvention are set forth in the following figures.

FIG. 1 illustrates a process according to some embodiments of theinvention.

FIG. 1A illustrates an exemplary result for each step in the process ofFIG. 1.

FIG. 2 illustrates an exemplary product of the method of someembodiments in further detail.

FIG. 3 illustrates a molded block in accordance with some embodiments.

FIGS. 4-12 illustrate cross section views taken on a side of a packagein accordance with some embodiments.

FIG. 4 illustrates a package having contact pads that are not at theedge of the package.

FIG. 4A illustrates a package having contact pads that are at the edgeof the package.

FIG. 5 illustrates a package having a die that is larger than its dieattach pad.

FIG. 5A illustrates a bottom view for the package of FIG. 5 having aring around the die attach pad.

FIG. 5B illustrates an alternate bottom view for the package of FIG. 5,which has a discontinuous ring around the die attach pad.

FIG. 6 illustrates a die overhanging its die attach pad.

FIG. 7 illustrates a die having a size that is close to the size of apackage.

FIG. 7A illustrates a die similar in size to its package such that thedie overhangs its die pad and the overhanging portion is bonded to thecontact pads.

FIG. 8 illustrates solder balls are optionally used to couple the die tothe contact pads.

FIG. 9 illustrates a package that is a hybrid of flip chip and wirebonding methods.

FIGS. 10-12 illustrate a stacked die implementation.

In particular, FIG. 10 illustrates stacked die where one die is smallerthan another die.

FIG. 11 illustrates stacked die that are approximately the same sizewith a spacer die.

FIG. 12 illustrates stacked die that are approximately the same sizewith epoxy instead of a spacer die.

FIGS. 13-17 illustrate various bottom view configurations for multipleembodiments of the invention.

In particular, FIG. 13 illustrates contact pads at the sides of a diepad, according to some embodiments.

FIG. 13A illustrates the package of FIG. 13 with the contact pads at theedge of the package.

FIG. 14 illustrates contact pads surrounding the periphery of the diepad.

FIG. 14A illustrates the package of FIG. 14 with the contact pads at theedge of the package.

FIG. 15 illustrates a die pad having an exposed center.

FIG. 15A illustrates an alternative configuration for the die pad andwith contact pads at the edge of the package.

FIG. 16 illustrates multiple rows of contact pads surrounding theperiphery of the die pad.

FIG. 16A illustrates the package of FIG. 15 with the outer most row ofcontact pads at the edge of the package.

FIG. 17 illustrates a guard band according to some embodiments.

FIG. 17A illustrates a guard ring in accordance with some embodiments ofthe invention.

FIG. 18 illustrates a semiconductor package in phantom view per anembodiment of this invention.

FIG. 19A illustrates a portion of a process for making the semiconductorpackage per an embodiment of this invention.

FIG. 19B illustrates a portion of a process for making the semiconductorpackage per an embodiment of this invention.

FIG. 20A illustrates a portion of a process for making the semiconductorpackage per an embodiment of this invention.

FIG. 20B illustrates a portion of a process for making the semiconductorpackage per an embodiment of this invention.

FIG. 21A illustrates a portion of a process for making the semiconductorpackage per an embodiment of this invention.

FIG. 21B illustrates a portion of a process for making the semiconductorpackage per an embodiment of this invention.

FIG. 21C illustrates a portion of a process for making the semiconductorpackage per an embodiment of this invention.

FIG. 22 shows a plated leadframe per an embodiment of this invention.

FIG. 23 shows platted leadframes having support structures per anembodiment of this invention.

FIG. 24 shows a sealant or passivation layer over a leadframe per anembodiment of this invention.

DETAILED DESCRIPTION

In the following description, numerous details and alternatives are setforth for purpose of explanation. However, one of ordinary skill in theart having the benefit of this disclosure will realize that theinvention can be practiced without the use of these specific details. Inother instances, well-known structures and devices are shown in blockdiagram form in order not to obscure the description of the inventionwith unnecessary detail.

I. Method

FIG. 1 illustrates a process 100 for manufacturing a semiconductorpackage according to some embodiments of the invention. FIG. 1Aillustrates an exemplary result for each step in the process 100 ofFIG. 1. As shown in these figures, the process 100 begins at the step110, where a metal layer 112 is formed. The metal layer typicallycomprises copper, Alloy 42, or another suitable metal material, and hasa typical thickness of about 0.1 to 0.15 millimeters. Then, after thestep 110, the process 100 transitions to the step 120, where particularareas on the metal layer 112 are plated. These areas typically includean area for a die pad 122 and a contact pad 124.

Once the particular areas on the metal layer 112 are plated, the process100 transitions to the step 130, where die attach and/or wire bondingoccur. As shown in FIG. 1A, die attach typically includes coupling a die132 to the die attach pad 122, while wire bonding includes using a wire134 to couple the die 132 to the die pad 122 and/or one or more contactpads 124.

After die attach and/or wire bonding occur at the step 130, the process100 transitions to the step 140, where a molding 142 is applied.Typically the molding 142 includes a plastic polymer or resin thatencapsulates the die 132, the wire bonds 134, the top surface of themetal layer 112, and the top surface of the plated areas, including thedie pad 122 and the contact pads 124.

Once the molding 142 is applied at the step 140, the process 100transitions to the step 150, where the metal layer 112 is removed. Someembodiments employ a chemical etchant to etch away the metal layer 112without affecting the plated areas (122 and 124) or the molding 142. Inthese embodiments, when the metal layer 112 is etched away, the bottomsurfaces of the plated areas, including the die pad 122, and the contactpads 124, are typically exposed.

At this point, some embodiments have formed a molded block 300 (see FIG.3) having exposed plated contact areas. Such a configuration hasparticular advantages in the industry. For instance, the molded block300 is advantageously employed for testing and other processes after thestep 150 of FIG. 1. The testing of some embodiments comprises aparallel, high speed, and/or bulk process for several of the deviceslocated within the molded block 300. The molded block 300 of theseembodiments is further described below in relation to FIG. 3.

Regardless of any testing and/or additional process steps after the step150 of FIG. 1, the process 100 typically transitions to the step 160,where individual units contained within the molded block 300 aresingulated to form individual semiconductor packages (see FIG. 2). Then,the process 100 transitions to the step 170, where the singulatedpackages are available for additional testing, processing, shippingand/or use. However, testing, handling, and/or processing of individualsingulated packages at the step 170, rather than by using the moldedblock 300 (available after the step 150), presents certaindisadvantages, as discussed below. After the step 170, the process 100concludes.

FIG. 2 illustrates an exemplary package 200 of the method of someembodiments in further detail. As shown in this figure, the exemplarypackage 200 has an exposed die attach pad 222, one or more contact pads224, a semiconductor die 232, one or more wire bonds 234, an adhesive236, and a molding compound 242. The adhesive 236 preferably couples thedie 232 to the die attach pad 222. The wire bonds 234 typically couplethe die 232 to one or more contact pads 224 and/or the die attach pad222.

Also shown in FIG. 2, the plating of some embodiments comprises multiplelayers. For instance, the plating layers of some embodiments includepalladium, nickel, and/or gold. In a particular embodiment, a firstlayer of palladium 250 has a minimum thickness of 0.5 micro meters, alayer of nickel 251 has a minimum thickness of 5.0 micro meters, asecond layer of palladium 252 has a minimum thickness of 0.1 micrometers, and a layer of gold 253 has a thickness of about 50 Angstroms.In some of these particular embodiments, the first layer of palladium islocated near an interior of the package for providing a coupling locusto the wire bond 234, while the gold plating is preferably located near,or is exposed near the bottom surface of the package 200, for providinga contact locus to a printed circuit board, or the like. The plated area(the die pad and contact pads) of these embodiments typically has atotal thickness in the range of about 6.0 micro meters to 12.0 micrometers. As mentioned above, the plated area(s) and the molding areminimally or not affected by the removal of the metal layer at the step150 of FIG. 1. For instance, when the metal layer comprises copper, andthe removal step 150 involves using a chemical etchant, preferably, theetchant and/or the plating structure are selected such that the etchantis reactive (removes) the metal layer with minimal effect to theplating. An example of such an etchant includes cupric chloride.

Also mentioned above, the molded blocks produced during the process 100have certain advantages for handling and additional processing, over theindividual singulated packages illustrated in FIG. 2. FIG. 3 illustratesa molded block 300 in accordance with some embodiments. As shown in thisfigure, the molded block 300 includes plated areas (that typicallyinclude die pads 322 and/or contact pads 324) for attaching potentiallymany semiconductor devices. Also shown in FIG. 3, the molded block 300has an attached metal layer 312 that was used for the plating andmolding (encapsulation) steps to generate the molded block 300. Asmentioned above, the metal layer 312 is preferably etched away to exposethe plated areas of the molded block 300.

The molded block 300 of these embodiments has certain advantages,particularly for the manipulation and testing of semiconductor devices.For instance, the molded block of a particular embodiment has dimensionsof approximately 1.77×2.0 inches, and includes approximately 250 to2,500 semiconductor units. This molded block, due to its moldingstrength and particular size, is configured for parallel processing ofsubstantially all of the semiconductor devices within the molded block,simultaneously. Conventionally, semiconductor device and/or packageprocessing includes time consuming operations, such as test, forexample. However, parallel processing of such operations advantageouslyenhances the speed and reliability of performing such operations, forbulk quantities.

II. Streamlined Process and Configuration Advantages

The process 100 described above, further includes additional advantages.For instance, due to the direct use of the metal layer and plated areas,and the subsequent removal of the metal layer to expose the platedareas, embodiments of the invention reduce the number of process stepsrequired for semiconductor package formation. This presents costsavings, and time savings, which present additional cost savings, overconventional methods. These and other advantages are discussed infurther detail below, in relation to the referenced figures.

FIGS. 4-17 illustrate various side and/or bottom view configurations formultiple embodiments of the invention. Some of these embodiments areformed by using the process 100 described above in relation to FIGS. 1and 1A. As illustrated in FIGS. 4-17, these packages have severaladvantages.

(1) For instance, as mentioned above, the process 100 has fewer steps offabrication than conventional methods known in the art. Because theprocess 100 has fewer steps, it is less expensive than the processesknown in the art. Moreover, because the process 100 has fewer steps, itis also generally faster than other processes, or, in other words, has ahigher throughput.

(2) The process 100 is capable of yielding package sizes that are closeto the dimension of the packaged die inside the package. The advantagesof reductions in package size are understood by those of ordinary skill.For example, a package having a footprint that is approximately its diesize will require a mounting area on a circuit board that is not muchgreater than approximately the size of the die. Thus, this advantageallows the placement of many more semiconductor devices on a board, orthe use of a smaller circuit board, which further typically results insmaller form factor applications, and additional size and/or costsavings, such as from reduced shipping and manufacturing costs, forexample.

(3) Further, a package having a thickness close to the die thicknessencapsulated inside the package allows for lower profile implementationsthat use such small outline and/or low profile packages.

(4) Because the critical factor regarding height for the packages formedby the process 100, is typically the height of the die, or anotherfactor, the height of the contact pads has no or negligible impact onthe height of the package. Effectively, the contact pads have a zero, oralmost zero, height in relation to the height of the package and/or thedie.

(5) Additionally, because the process 100 has fewer steps, and itsproducts are typically close in size to the small encapsulated die, thepackages illustrated and described herein provide savings in the volumeof construction materials consumed over time, or, in other words,provide a higher yield. Moreover, the various many possible packageconfigurations enabled by the process 100 described above, yield furtheradvantages, as discussed below.

III. Side (“Cross Section”) Views of Exemplary Package Designs

FIGS. 4-12 illustrate a cross section (side view) of the package of someembodiments. For instance, FIG. 4 illustrates a package 400 havingcontact pads 424 that are not at the edge of the package 400, while FIG.4A illustrates a package having contact pads 424 that are at the edge ofthe package 400. Some embodiments alternatively select whether thecontact pads 424 should be placed at the edge of the package 400. Someembodiments of the process 100 illustrated in FIGS. 1 and 1A above,account for the position of the contact pads 424 at the step 120(plating) and/or the step 150 (singulation). As an example, someembodiments plate areas for the contact pads of two adjacent packagesclose together during the plating step 120 of FIG. 1. Then, during thesingulation step 150 of FIG. 1, these embodiments singulate or removethe entire molding and unplated regions between the two contact pads,such that the resultant two separate packages to the left and right ofthe singulation cut have contact pads that are at the edge of thepackage. These packages are typically smaller in size and have aslightly smaller footprint due to the maximum use of the edge of thepackage for the contact pad. Hence, and as additionally shown in FIGS. 4and 4A, the decision whether the contact pads 424 are placed at edge ofthe package 400, or not, affects the overall footprint and spaceavailable within and at the bottom footprint of the package 400.

Some embodiments have various additional configurations for the contactpads and the die pad that vary, in some aspects, in relation to the die.For instance, FIG. 5 illustrates a package 500 having a die 532 that islarger than its die attach pad 522. As shown in this figure, the die 532of some of these configurations overhangs the die pad 522. In theseconfigurations, an adhesive 536 typically used to secure the die 532 tothe die pad 522, often spans the surface of the die pad 522 and spillsover to engulf the surfaces of the die pad 522 that are not shielded bythe metal layer during the encapsulation step (140 of FIG. 1). Due tothe additional space between the die pad 522 and the edge-locatedcontact pads 524, some of these configurations further include anadditional plated ring around the die pad 522. Some of these rings arecontinuous, while some are discontinuous around the die pad 522. FIG. 5Aillustrates a bottom view for the package 500 of FIG. 5 having a ring523 around the die pad 522. FIG. 5B illustrates an alternate bottom viewfor the package 500 of FIG. 5, which has a discontinuous ring 523 aroundthe die attach pad 522.

These plated areas 523 between the die pad 522 and the contact pads 524provide additional plated areas for electrical contact and/or heattransfer for the package 500. Some embodiments, for instance, couple thedie to the plated ring, particularly where the die overhangs the diepad, while some embodiments forego the die pad altogether in favor ofthe plated ring of these embodiments. More specifically, the purpose ofthe plated ring of particular embodiments is that some die designs, suchas the “ground bond” design, require a connection between a top surfaceof the die, and a ground of the printed circuit board. In theseembodiments, the plated ring 523 provides the grounding point for theprinted circuit board. Some designs require a connection between a topsurface of the die, and both the plated ring area 523 and a contact pad524. These designs, often referred to as “down bond” designs, typicallyinclude a wire bond between the plated ring 523, and the contact pad 524(not shown).

In additional embodiments, when the die overhangs the die pad, the dieis attached to the die pad and is also advantageously attached to aportion of one or more contact pads. FIG. 6 illustrates such anembodiment where a die 632 that overhangs its die pad 622 is furtherattached to one or more contact pads 624. As shown in this figure, anadhesive 636 attaches the die 632 to both the die pad 622 and to theportions of the contact pads 624 that underlie the overhanging sides ofthe die 632.

In some of the embodiments described above, or in other embodiments, thedimensions of the die approaches the size of the package. In otherwords, for very small packages, or for large die in relation to the sizeof the package, it is advantageous to optionally omit the die padaltogether. FIG. 7 illustrates such a package 700 that includes a die732 having a size that is close to the size of the package 700. As shownin this figure, the die pad is omitted, such as during the plating step120 of FIGS. 1 and 1A, above. In these embodiments, the omission of thedie pad advantageously contributes to a reduction in form factor for thepackage 700.

However, in some embodiments, it is often still desirable to provideexternal contact to the die pad, such as for electrical contact and/orheat dissipation, for example. FIG. 7A illustrates a die 732 having asimilar size to a package 700, where the die 732 extends over thecontact pads 724 and is bonded to the contact pads 724 by the adhesive736.

FIG. 8 illustrates that not only bond wires, but also solder balls 835are (alternatively) applied for electrical connection between the die832 and the contact pads 824 of alternative embodiments. This is alsosometimes known as a flip chip style package.

FIG. 9 illustrates that some embodiments have multiple dice 932 and 933,which are stacked by using a hybrid of flip chip and wire bondtechniques. Accordingly, the die 932 is coupled to the contact pads 924by using solder balls 935 in the flip chip style, while the die 933 iscoupled to the contact pads 924 by using bond wires 934. Further, thedie 932 is coupled to the die 933 by using an adhesive 936.

Stacked Die

The packages of the embodiments described above further allow for a“stacked die” package configuration. Multiple and/or stacked diesignificantly increase the number of alternative configurations. FIGS.10-12 illustrate some exemplary stacked die implementations inaccordance with embodiments of the invention.

More specifically, FIG. 10 illustrates a daughter die 1033 that has asmaller size than a mother die 1032. As shown in this figure, the die1033 is attached to the die 1032, which is attached to a die pad 1022.Typically, the attachment is by an adhesive 1036, while bonding wires1034 couple the dice 1032 and 1033 to one or more contact pads 1024.

FIG. 11 illustrates a case where the daughter die 1133 and the motherdie 1132 have the same approximate size. In these embodiments, a spacerdie 1131 is advantageously inserted between the two stacked dice 1132and 1133. As shown in the figure, the spacer die 1131 permits access tothe die 1132 such that bond wires 1134 couple the die 1132 to thecontact pads 1124.

FIG. 12 illustrates another option when the daughter die 1233 and themother die 1232 have the same approximate size. In this configuration,an adhesive 1236 is applied directly between the two dice 1232 and 1233,instead of a spacer die. The adhesive 1236 of these embodiments includesan epoxy such as that used for die attach to a die pad, or anotherthermal, electrical, and/or adhesive material. As shown in FIG. 12, theadhesive advantageously permits access to the die 1232, such as by thebond wire 1234, for example.

IV. Bottom (“Floor Plan”) Views

FIGS. 13-17 illustrate bottom views of the connector and/or mountingside of some of the packages described above.

More specifically, FIG. 13 illustrates a package 1300 that has contactpads 1324 at the sides of a die pad 1322. In this type of package 1300,the heat which is generated by the encapsulated semiconductor device(1332) during operation of the device (1332), is preferably transferredto the PCB via the die pad 1322. FIG. 13A illustrates the package 1300of FIG. 13, with the contact pads 1324 at the edge of the package 1300.

FIG. 14 illustrates a package 1400 that has contact pads 1424 at theperiphery of the die pad 1422. Moreover, these contact pads 1424surround the die pad 1422 for achieving the benefit of higher pin countsin the small area of the package 1400. In FIG. 14, the contact pads 1424are not at the edge of the package 1400, while in FIG. 14A, the contactpads 1424 are at the edge of the package 1400.

FIGS. 15 and 15A illustrate an alternative configuration for the die padof FIG. 14. In FIG. 15, the die pad 1522 comprises a plated ring with anexposed center, while in FIG. 15A the die pad 1522 comprises a platedring with a central plated portion attached to the ring with fourconnecting bars.

FIG. 16 also illustrates contact pads 1624 at the periphery of the diepad 1622, but in more than one perimeter or circumference around the diepad 1622. This implementation typically yields even higher pin countsfor the small package 1600.

FIG. 17 illustrates contact pads 1724 at a periphery of the die pad 1722with a security guard band 1725. As shown in this figure, someembodiments have only one guard band 1725. However, the package 1700 ofother embodiments employ more than one guard band 1725. In fact, theguard band of some embodiments fully surrounds the die pad 1722, as aguard ring. FIG. 17A illustrates such an embodiment having contact pads1724 at a periphery of the die pad 1722 with a security guard ring 1726.

The guard band 1725 and/or guard ring 1726 of these embodiments takeadvantage of and/or enable reduced contact pad height. As mentionedabove, the contact pad height of some embodiments is zero, or almostzero. Some applications in the security field require an “unable” totest signal from the bottom of the package after installing the packageon a PCB. The security guard band and/or ring is an additional (double)security measure that protects against having an open space, and/orseparation of the package from the PCB during the insertion of a testsignal probe between the (bottom of the) package and the PCB upon whichthe package is typically (surface) mounted. More specifically, theadditional plated and/or metal soldering area for securing the packageto the PCB, protects the contact pads and/or die pad of the package fromundesirably separating from the PCB during handling, test, or anothersimilar type of operation.

V. Plated Ball Grid Array

FIG. 18 shows a plated ball grid array package 1800 in phantom view. Thepackage 1800 comprises a semiconductor die 1810 having an active surfacefacing up toward the viewer and an inactive surface facing down. Theactive surface has several wirebonding pads 1820. These wirebonding pads1820 serve as input/outputs for the semiconductor die 1810, for exampleproviding power, control, inputs signals, desired outputs, and the like.The package 1800 further comprises a plurality of contact traces 1830.The contact traces 1830 each have a first end 1832 and a second end1835. A bondwire 1840 is mounted to at least some of the first ends 1832and to the wirebonding pads 1820 for forming an electrical connectionbetween the die and the contact traces 1830 as desired. The second ends1835 are configured with solder balls or solder bumps as explained belowto form an electrical contact with an end application, usually a printedcircuit board. The contact traces 1830 are arranged substantiallyunderneath the semiconductor die 1810. This arrangement allows for theoverall package 1800 to be only slightly larger than the semiconductordie 1810 itself. Furthermore, the contact traces 1830 are formed byplating methods described above. Also, the semiconductor die 1810 can bemade extremely thin by die grinding techniques (sometimes known asbackgrinding) that are able to produce semiconductor die that arefractions of millimeters thick. As a result, what is achieved is ahighly thin, very small semiconductor package 1800.

FIG. 19A shows some steps of a the process 1900 for forming thesemiconductor package 1800 of FIG. 18. In a first step 1910, a metalsubstrate, preferably copper, is provided. In a later step 1920, adesired pattern of traces is plated upon the metal substrate. In a laterstep 1930, semiconductor die are mounted on the metal substrate abovethe traces and wirebonds are mounted to form electrical contacts asdescribed above in FIG. 18. In a later step 1940, the substrate,semiconductor die, wirebonds, and contact traces are encased in a moldcompound. In a step 1950, the metal substrate is sacrificed, leaving thecontact traces visible in the later step 1960.

In some embodiments, the process moves on to FIG. 19B. Although a singlesemiconductor package 1800 is shown, the person of ordinary skill havingthe benefit of this disclosure will appreciate that the semiconductorpackages are still in matrix form as in FIGS. 18 and 19A. FIG. 19B showsthe semiconductor package 1800 of FIG. 18 having a solder resist epoxyapplied thereon. In a step 1970, a screen 1971 is placed over surface ofthe semiconductor device 1800 having the contact traces thereon. Thescreen stencil 1971 has a permeable area 1971A that is permeable by aliquid substance and an impermeable area 1971B that is impermeable by aliquid substance. Preferably, the impermeable area 1971B is arrangedsuch that it falls on the second ends of the contact traces 1835 of FIG.18. In a later step 1980, solder resist epoxy 1981 is placed at one endof the semiconductor package 1800 and is smeared across thesemiconductor package 1800 by a trowel 1985. The impermeable areas 1971Bprevent the solder resist 1981 from coating the second ends of thecontact traces 1835 of FIG. 18. In a later step 1990, a UV cure light1992 cures the solder resist epoxy. What results in a step 1995 is asemiconductor package 1800 having a solder resist epoxy layer 1998having openings 1999 for placing solder bumps or solder balls asexplained further below. Alternatively, a solder resist film can be usedrather than a solder resist epoxy over a screen stencil as shown in FIG.20A.

In FIG. 20A, the semiconductor package 1800 is shown having a solderresist film applied thereon. The solder resist film 2015 is shown beinglowered onto the semiconductor package 1800 in a step 2010. In a laterstep 2020, the solder resist film 2015 is applied to the semiconductorpackage 1800 by some means for applying pressure. In the example of FIG.20A, a rolling pin 2025 is shown. Those of ordinary skill having thebenefit of this disclosure will recognize several means and methods ofapplying the solder resist film 2015 onto the semiconductor package1800. In a later step 2030, the solder resist film 2015 is cured by UVlight from a UV light source 2032. The process continues in FIG. 20B. Ina step 2040, the semiconductor package 1800 is dipped into a vat 2045having etching material 2048. During exposure to the developmentmaterial 2048, portions that are uncovered by the solder resist film2015 are exposed to the etching material 2048. After exposure, thoseportions are removed. In a later step 2050, the solder resist film 2025is cured. In the example provided, heating elements 2055 provide heatfor the curing step.

FIGS. 21A and 21B show exemplary process steps of attaching solder bumpballs to the semiconductor package per an embodiment of this invention.FIG. 21A shows the process steps of implementing a screen for applyingsolder bump balls. In a step 2110, a screen is placed over thesemiconductor package 1800. The screen 2115 has a solid metal area 2117that is impenetrable by liquid solder, and an array of openings 2118.Preferably, the openings 2118 are positioned such that when the screen2115 is placed over the semiconductor device 1800, the openings 2118coincide with the second ends of the contact pads 1835 of FIG. 18. In alater step 2120, solder paste is applied. In some embodiments, thesolder paste is in mix of solder and flux. The solder paste rolls offthe solid metal area 2117 and settles in the portions left bare by theopenings 2118. What results is a solder paste bump 2125 that iselectrically coupled to the second end of the contact trace 1835 of FIG.18. In a later step 2130, heat is applied to the solder paste bumps2125, causing the flux within the solder paste to flow away, and thesolder paste bump 2125 melts and assumes a round shape. What results isa solder bump ball 2135. The solder bump ball 2135 serves as an adhesiveand a means for forming an electrical contact with an end application,such as a printed circuit board. FIG. 21B shows an alternate process forforming solder bump balls. An extruder 2145 drops solder flux 2147 intothe areas not covered by the solder resist film 2025 of FIGS. 20A and20B. As described above, these portions coincide with the second ends ofthe contact traces 1835 of FIG. 18. Then, solid solder balls 2155 areplaced above the solder flux 2147. In one exemplary method, thesemiconductor package 1800 is agitated or vibrated while solder ballsare poured upon the surface having the solder resist film 2025.Eventually, all the portions having solder flux 2147 are filled with asolder ball 2155 when the solder ball 2155 becomes stuck in the solderflux 2147. In a later step 2160, the solder balls 2155 are exposed toheat 2165, forcing out the flux 2147 and causing the solder balls tomelt and assume a form fitting shape into the open portions. Finally, ina singulation step 2170, a saw 2175 separates the matrix and anindividual semiconductor package 1800 is formed.

VII. Support Structures

As discussed above, current technologies require a large number of I/Oavailable for a semiconductor device. Semiconductor packages having agreater number of I/O, or contact points, have been developed. However,with increased number of I/O comes an increase in the form factor. Tothat end, a high density plated pattern of contact traces per anembodiment of this invention is shown in FIG. 22. A metal substrate2200, such as copper, has several contact traces 2210 plated thereon bya process such as the one described in the above Figures. The contacttraces 2210 have several end points 2211 for making multiple externalcontacts with. This allows for greater density of I/O in a finalapplication. However, as density increases, the contact traces 2210 aremade thinner, which may lead to the contact traces 2210 peeling from thesemiconductor package as the package is heated during the reflow stepsmentioned above or when the semiconductor package is heated during alater mounting step.

To that end, FIG. 23 shows the traces 2210 and end points 2211 of FIG.21 having various support structures to reduce peeling during processsteps in manufacturing and application that involve heating thesemiconductor package. FIG. 23 shows one embodiment wherein theperimeter of the contact trace 2310 comprises several support structures2315 emanating outward therefrom. The support structures 2315 increasethe adhesion of the contact traces 2310 to the eventual semiconductordie when it is completed. In the example provided, the supportstructures 2315 are represented as generally rectangular protrusionsintegrated with the contact trace 2310. However, the person of ordinaryskill having the benefit of this disclosure will recognize that manyshapes can be used as applications require. The shape should be chosen,among other factors, according to how densely the contact traces 2310are placed and the size of the semiconductor die that is to be used. Theshapes can have linear features, such as the rectangles shown, orarcuate features, such as half circuits, ovoids, or any other roundedshape. FIG. 23 shows exemplary support structures for the ends of thecontact traces. The first (right topmost) image shows a bare contacttrace end 2320, similar to the second end 1835 of FIG. 18. In someapplications, an enlarged area at the end of the contact trace 2310suffices as a support structure to prevent peeling. In the embodimentshown, the enlarged area is bulbous and round, but as mentioned abovecan take any appropriate shape for a particular application. The secondimage, below the first image, shows three additional support structuresemanating from the contact end 2320. The exemplary shapes of the supportstructures 2330 are linear in nature and form three Ts. The third image,below the second image, shows “Y” shapes for the support structures2340. Although a greater area consumed by the support structures 2340can further reduce the likelihood of peeling, the greater area alsoreduces the available surface area for a maximum density of the contacttraces 2310. To that end, the last (right bottommost) image shows anarcuate support structure 2350. Advantageously, the arcuate supportstructure 2350 provides more surface area for contacting the moldcompound (not shown) and thereby providing greater adhesion. In theexample shown, the support structure 2350 completely circumscribes thecontact trace end 2320 and is integrated by tying bridges 2355. However,the arcuate support structure 2350 can also be shaped such that itpartially circumscribes the contact trace end 2320. Advantageously, allof these support structures mentioned can be plated along with thecontact traces 2310 in the same process steps as described in theprevious Figures. The plating patterns discussed above, such as in step1920 of FIG. 19 can be altered to include the support structures. As aresult, no additional process steps are needed to include the supportstructures, and only an incremental increase in materials. As a result,any cost increase due to the support structures will be insignificant.

In general, end manufacturers that use semiconductor devices in packagessuch as the one described in the above drawings have a certain pitchrequirement between contact traces and the ends of the contact traces.In general, a semiconductor package has solder bumps or balls mounted ona surface that contacts an end application, such as a printed circuitboard. The semiconductor package is heated to melt the solder which thenmakes a physical and electrical connection with the end application.However, end users' manufacturing tolerances vary widely, and as aresult some minimum distance, or pitch between the contact traces ortheir ends is specified by the end user. As can be seen from theembodiments of FIG. 23, the support structures can cause the contacttraces and their ends to be closer together. To that end, the solderflux screening methods shown in FIGS. 19B-20B preferably have openings(such as 1999 of FIG. 19) that conform to the pitch requirements of anend user. FIG. 24 shows the semiconductor device 1800 having the solderresist layer 1998 (from FIGS. 18 and 19, respectively). As an example,the support structure 2330 of FIG. 23B is shown under the solder resistlayer 1998. Although a solder resist layer is shown and discussedherein, those of ordinary skill having the benefit of this disclosurewill readily recognize that other passivation means and methods can beemployed to form an electric separation between the semiconductor die1800 and an end application or to form a barrier to solder. The opening2400 in the solder resist layer can be made smaller than the end of thecontact trace. Alternatively, another opening 2410 is shown being thesame size as the end of the contact trace 2410. Still alternatively, theopening 2420 is larger. In some embodiments, the size of the openings2400, 2410, and 2420 is determined by the pitch requirement of the enduser.

While the invention has been described with reference to numerousspecific details, one of ordinary skill in the art will recognize thatthe invention can be embodied in other specific forms without departingfrom the spirit of the invention. Thus, one of ordinary skill in the artwill understand that the invention is not to be limited by the foregoingillustrative details, but rather is to be defined by the appendedclaims.

What is claimed is:
 1. A method of forming a semiconductor packagecomprising: a. plating a plurality of contact traces on a metalsubstrate, each contact trace having a first end and a second end and apathway between the first end and the second end, wherein the first endis wider than the pathway; b. mounting semiconductor die substantiallyabove the second ends of the contact traces; c. electrically couplingthe semiconductor die to at least one first end of at least one contacttrace; d. encapsulating the semiconductor die in an encapsulant; e.removing the metal substrate, thereby exposing the contact traces; andf. singulating the semiconductor package.
 2. The method of claim 1,further comprising forming at least one support structure about thesecond end of at least one contact trace.
 3. The method of claim 2,wherein forming support structures comprises forming at least one platedarea extending outward from the second end of the at least one contacttrace.
 4. The method of claim 2, wherein forming support structurescomprises forming at least one plated area substantially circumscribingthe second end of the at least one contact trace.
 5. The method of claim2, wherein forming support structures comprises forming at least oneplated area having a substantially arcuate shape.
 6. The method of claim2, wherein forming support structures comprises forming at least oneplated area having a substantially linear shape.
 7. The method of claim1, wherein the metal substrate comprises copper.
 8. The method of claim1, wherein plating a plurality of contact traces comprises platinglayers comprising palladium, gold, and nickel.
 9. A method of forming asemiconductor package comprising: a. plating a plurality of contacttraces on a metal substrate, wherein the contact traces comprise aplurality of plated layers, each contact trace having a first end and asecond end and a pathway between the first end and the second end,wherein the first end is wider than the pathway; b. electricallycoupling a first semiconductor die substantially above at least aportion of the contact traces; d. encapsulating at least a portion ofthe plurality of contact traces and the first semiconductor die in anencapsulant; e. removing the metal substrate, thereby exposing thecontact traces; and f. singulating the semiconductor package.
 10. Themethod of claim 9, further comprising coupling a second semiconductordie with the first semiconductor die, wherein the second semiconductordie is coupled with the first end of at least one contact trace by abondwire.
 11. The method of claim 9, further comprising coupling asecond semiconductor die with the first semiconductor die, wherein thesecond semiconductor die is coupled with the first end of at least onecontact trace by a solder bump.
 12. The method of claim 9, furthercomprising coupling a second semiconductor die with the firstsemiconductor die by a bondwire.
 13. The method of claim 9, furthercomprising coupling a second semiconductor die with the firstsemiconductor die by a solder bump.
 14. The method of claim 9, furthercomprising plating a die attach pad on the metal substrate, wherein thedie attach pad receives the first semiconductor die, wherein the dieattach pad comprises a plurality of plated layers.
 15. A method offorming a semiconductor package comprising: a. plating a plurality ofcontact traces on a metal substrate, wherein the contact traces comprisea plurality of plated layers, each contact trace having a first end anda second end and a pathway between the first end and the second end,wherein the first end is wider than the pathway; b. electricallycoupling the first end of at least one contact trace to an activesurface of a semiconductor die; d. encapsulating at least a portion ofthe semiconductor die and plurality of contact; e. removing the metalsubstrate, thereby exposing the contact traces; and f. singulating thesemiconductor package.
 16. The method of claim 15, wherein the plating aplurality of contact traces includes forming a plurality of supportsabout the second ends of the plurality of contact traces.
 17. The methodof claim 16, wherein the at least one support structure includes arectangular protrusion integrated with the contact trace.
 18. The methodof claim 15, wherein the pathway has at least one support structure thatemanates outward therefrom.
 19. The method of claim 15, wherein acontact pad is located at the first end and an end point is located atthe second end.
 20. The method of claim 15, further comprising applyingsolder resist epoxy on a side with the exposed contact traces withoutcoating each second end in its entirety.